Modern integrated circuits have become very dense and complex. For example, state-of-the art integrated circuits constituting processors may each include many millions of transistors and other components. There are software logic equation generation and analysis tools for extracting logic equations from a circuit description and providing certain preliminary analysis. This is a routine procedure carried out early in the logic design of a complex digital system component. However, checking the resulting logic equations of, for example, a processor for subtle errors is a very formidable problem which is impossible to carry out manually and difficult to achieve with any test software.
It might be thought that all possible errors could be found by exercising exhaustive combinations of inputs, outputs and operations sequentially, with test software, on the logic equations representing the design, but, even with a high speed test program running on a powerful machine, the time required is prohibitive and adequate coverage cannot be achieved. As a result, a class of advanced logic analysis programs have been developed which first examine the logic equations and reduce them before analyzing all possible combinations in a search for possible design errors. The processes of these advanced analysis programs are variously known as formal proof, equivalence proof, equivalence checking, formal verification, formal validation, property checking, etc. (For convenience, the term “formal proof” is used herein as a generic term for these types of programs.) While formal proof programs may still take a long time to analyze all combinations of the reduced logic, the time is not prohibitive for use during the development and analysis of a complex logic component.
In the preliminary analysis phase of logic circuits by logic equation generation and analysis programs, violations of “loading” and “drive” restrictions for driving nodes and other similar analyses are made. These analyses are typically based upon absolute worst-case assumptions which is necessary because the program doing the analysis typically does not “know” the logic states or have a list of the legal conditions which might control or restrict the operation of the logic circuit under “real” conditions. These absolute “worst case” assumptions involve no analysis of the logical state of a circuit and simply look for violations of loading rules while making the assumption that all possible loads are “actively loading” a specific driving circuit at all times. But, this absolute worst-case assumed solution may be much too pessimistic in that, in all “real” possible combinations for a given driving node, some of the loads may be through transistors which are not enabled such that the actual worst case loading might be less or even much less. This characteristic leads to warnings or error reports, from circuit analysis programs, which are in fact not “real” or possible during the actual operation of the logic circuit. The logic even of a single driving node may be too complicated to analyze easily by hand, and/or the number of warnings/errors reported may obscure the recognition of “real” errors; i.e., the important message may be buried in a report containing a large number of “false” errors.
While the absolute worst-case assumed solution provides a safely operable power handling capability for a given driving node, significant disadvantages are that when the design is implemented in hardware, more “real estate” area on the complex logic circuit's actual integrated circuit(s) and the resulting false need for a larger driving transistor slows down the actual operation of the circuit.
Thus, it will be appreciated by those skilled in the art of logical design of complex digital circuits that it wold be highly desirable to provide an efficient way to analyze the largest real loading of each and every driving node and to use that information to more correctly report upon violations in the power requirements for the driving transistor and to aid in properly sizing the transistors. This proper sizing may result in a circuit of less area and higher speed.